This invention relates to microcode control memory for computer systems. This invention finds particular application to very high-speed computers where the instruction cycle time of the computer is very fast compared to the memory recall time of the memory devices in the microcode memory. In particular, this invention relates to a plural microcode memory where a first memory receives and executes initial instructions of multistep instructions and the entire instruction for single step instructions and in which a plurality of additional memories provide instruction execution for multistep instructions.
There is extensive art in the field of control functions for computer mainframes and for microcode control systems. Some patents known to applicant show various methods of speeding up or increasing the rate at which a microcode control memory may function. One patent in this field which appears relevant to the present application is U.S. Pat. No. 4,080,648. This patent shows a microprogram control system using two memories. The first microcode instruction is applied to a control register as soon as a first instruction is fetched. The second memory is used in performing certain functions in the system shown in that patent. However, it is believed that the disclosure of this application is distinct from that of the patent. The present invention relates to a fast output selection network scheme for all memories in a microcode control system so that the memory output to be selected is controlled by a separate select network at the same time that the memory is outputting the control bits in response to an input instruction so that these two functions occur at the same time. The technique results in not only the fastest possible method of memory select control but also in a design which allows each memory or pairs of memories to be independent from each other while sharing the same output select network and thus supplying control signals to the same central processer unit. This fast response of memory select to hardware stimuli and memory independence are necessary when utilizing microcode control in the design of a high-speed, pipelined computer. In this case, the microcode control unit must provide stop, start, issue and control of an instruction stream in a pipeline or parallel fashion.